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HI5660
Data Sheet July 2004 FN4521.7
8-Bit, 125/60MSPS, High Speed D/A Converter
The HI5660 is an 8-bit, 125MSPS, high speed, low power, D/A converter which is implemented in an advanced CMOS process. Operating from a single +3V to +5V supply, the converter provides 20mA of full scale output current and includes edge-triggered CMOS input data latches. Low glitch energy and excellent frequency domain performance are achieved using a segmented current source architecture. For an equivalent performance dual version, see the HI5628. This device complements the HI5X60 family of high speed converters offered by Intersil, which includes 8, 10, 12, and 14-bit devices.
Features
* Throughput Rate . . . . . . . . . . . . . . . . . . . . . . . . 125MSPS * Low Power . . . . . . . . . . . . . . . 165mW at 5V, 27mW at 3V * Power Down Mode. . . . . . . . . . 23mW at 5V, 10mW at 3V * Integral Linearity Error . . . . . . . . . . . . . . . . . . . 0.25 LSB * Adjustable Full Scale Output Current . . . . . 2mA to 20mA * SFDR to Nyquist at 10MHz Output . . . . . . . . . . . . . 60dBc * Internal 1.2V Bandgap Voltage Reference * Single Power Supply from +5V to +3V * CMOS Compatible Inputs * Excellent Spurious Free Dynamic Range * Pb-free Available
Ordering Information
PART NUMBER HI5660IB HI5660IBZ (Note) HI5660/6IA HI5660/6IA-T TEMP. RANGE (C) PACKAGE PKG. CLOCK DWG. # SPEED M28.3 M28.3 125MHz 125MHz
Applications
* Medical Instrumentation * Wireless Communications * Direct Digital Frequency Synthesis
-40 to 85 28 Ld SOIC -40 to 85 28 Ld SOIC (Pb-free) -40 to 85 28 Ld TSSOP
M28.173 60MHz
* Signal Reconstruction * Test Instrumentation * High Resolution Imaging Systems * Arbitrary Waveform Generators
28 Ld TSSOP Tape and Reel M28.173 60MHz M28.173 60MHz
HI5660/6IAZ (Note) -40 to 85 28 Ld TSSOP (Pb-free) HI5660/6IAZ-T (Note) HI5760EVAL1
28 Ld TSSOP Tape and Reel M28.173 60MHz (Pb-free) 25 Evaluation Platform 125MHz
Pinout
HI5660 (SOIC, TSSOP) TOP VIEW
D7 (MSB) 1 D6 2 D5 3 D4 4 D3 5 D2 6 D1 7 D0 (LSB) 8 DCOM 9 DCOM 10 DCOM 11 DCOM 12 DCOM 13 DCOM 14 28 CLK 27 DVDD 26 DCOM 25 NC 24 AVDD 23 NC 22 IOUTA 21 IOUTB 20 ACOM 19 COMP1 18 FSADJ 17 REFIO 16 REFLO 15 SLEEP
NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J Std-020B.
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2000, 2004. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
HI5660 Typical Applications Circuit
HI5660 (15) SLEEP DCOM (9-14, 25) (16) REFLO (17) REFIO D7 D6 D5 D4 D3 D2 D1 D0 D7 (MSB) (1) D6 (2) D5 (3) D4 (4) D3 (5) D2 (6) D1 (7) D0 (LSB) (8) CLK (28) 50 DCOM (26) FERRITE BEAD 10F + 10H 0.1F DVDD (27) (23) NC (19) COMP1 (20) ACOM (24) AVDD 0.1F FERRITE BEAD 10H 0.1F + +5V OR +3V (VDD ) 10F 50 (21) IOUTB D/A OUT (22) IOUTA 50 (18) FSADJ RSET D/A OUT 1.91k 0.1F DCOM ACOM
Functional Block Diagram
IOUTA IOUTB
(LSB) D0 D1 D2 D3 D4 D5 D6 (MSB) D7 UPPER 5-BIT DECODER 31 LATCH LATCH 34 SWITCH MATRIX 34
CASCODE CURRENT SOURCE
3 LSBs + 31 MSB SEGMENTS
COMP1 CLK INT/EXT VOLTAGE REFERENCE BIAS GENERATION
INT/EXT REFERENCE SELECT
AVDD
ACOM
DVDD
DCOM
REFLO
REFIO
FSADJ SLEEP
2
HI5660
Absolute Maximum Ratings
Digital Supply Voltage DVDD to DCOM . . . . . . . . . . . . . . . . . +5.5V Analog Supply Voltage AVDD to ACOM. . . . . . . . . . . . . . . . . . +5.5V Grounds, ACOM TO DCOM . -0.3V To +0.3V Digital Input Voltages (D9-D0, CLK, SLEEP) . . . . . . . . . . . . . . . . . . . . . . . . . DVDD + 0.3V Internal Reference Output Current. . . . . . . . . . . . . . . . . . . . . 50A Reference Input Voltage Range. . . . . . . . . . . . . . . . . . AVDD + 0.3V Analog Output Current (IOUT) . . . . . . . . . . . . . . . . . . . . . . . . . 24mA
Thermal Information
Thermal Resistance (Typical, Note 1) JA(oC/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 TSSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC (SOIC - Lead Tips Only)
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER SYSTEM PERFORMANCE Resolution Integral Linearity Error, INL Differential Linearity Error, DNL Offset Error, IOS Offset Drift Coefficient Full Scale Gain Error, FSE
AVDD = DVDD = +5V, VREF = Internal 1.2V, IOUTFS = 20mA, TA = 25oC for All Typical Values TA = -40oC TO 85oC TEST CONDITIONS MIN TYP MAX UNITS
8 "Best Fit" Straight Line (Note 7) (Note 7) (Note 7) (Note 7) With External Reference (Notes 2, 7) With Internal Reference (Notes 2, 7) -0.5 -0.5 -0.025 -10 -10 2 (Note 3) -0.3
0.25 0.25
+0.5 +0.5 +0.025
Bits LSB LSB % FSR ppm FSR/oC % FSR % FSR ppm FSR/oC ppm FSR/oC mA V
0.1 2 1 50 100 -
+10 +10 20 1.25
Full Scale Gain Drift
With External Reference (Note 7) With Internal Reference (Note 7)
Full Scale Output Current, IFS Output Voltage Compliance Range DYNAMIC CHARACTERISTICS Maximum Clock Rate, fCLK Output Settling Time, (tSETT) Singlet Glitch Area (Peak Glitch) Output Rise Time Output Fall Time Output Capacitance Output Noise IOUTFS = 20mA IOUTFS = 2mA (Notes 3, 9) 0.8% (1 LSB, equivalent to 7 Bits) (Note 7) 0.4% (1/2 LSB, equivalent to 8 Bits) (Note 7) RL = 25 (Note 7) Full Scale Step Full Scale Step
125 -
5 15 5 1.5 1.5 10
-
MHz ns ns pV*s ns ns pF
-
50 30
-
pA/ Hz pA/ Hz
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HI5660
Electrical Specifications
PARAMETER AC CHARACTERISTICS HI5660IB, HI5660IA - 125MHz Spurious Free Dynamic Range, SFDR Within a Window Total Harmonic Distortion (THD) to Nyquist Spurious Free Dynamic Range, SFDR to Nyquist fCLK = 125MSPS, fOUT = 32.9MHz, 10MHz Span (Notes 4, 7) fCLK = 100MSPS, fOUT = 5.04MHz, 4MHz Span (Notes 4, 7) fCLK = 100MSPS, fOUT = 2.00MHz (Notes 4, 7) fCLK = 125MSPS, fOUT = 32.9MHz, 62.5MHz Span (Notes 4, 7) fCLK = 125MSPS, fOUT = 10.1MHz, 62.5MHz Span (Notes 4, 7) fCLK = 100MSPS, fOUT = 40.4MHz, 50MHz Span (Notes 4, 7) fCLK = 100MSPS, fOUT = 20.2MHz, 50MHz Span (Notes 4, 7) fCLK = 100MSPS, fOUT = 5.04MHz, 50MHz Span (Notes 4, 7) fCLK = 100MSPS, fOUT = 2.51MHz, 50MHz Span (Notes 4, 7) AC CHARACTERISTICS HI5660/6IA - 60MHz Spurious Free Dynamic Range, SFDR Within a Window fCLK = 60MSPS, fOUT = 10.1MHz, 10MHz Span (Notes 4, 7) fCLK = 50MSPS, fOUT = 5.02MHz, 2MHz Span (Notes 4, 7) fCLK = 50MSPS, fOUT = 1.00MHz, 2MHz Span (Notes 4, 7) Total Harmonic Distortion (THD) to Nyquist Spurious Free Dynamic Range, SFDR to Nyquist fCLK = 50MSPS, fOUT = 2.00MHz (Notes 4, 7) fCLK = 50MSPS, fOUT = 1.00MHz (Notes 4, 7) fCLK = 60MSPS, fOUT = 20.2MHz, 30MHz Span (Notes 4, 7) fCLK = 60MSPS, fOUT = 10.1MHz, 30MHz Span (Notes 4, 7) fCLK = 50MSPS, fOUT = 20.2MHz, 25MHz Span (Notes 4, 7) fCLK = 50MSPS, fOUT = 5.02MHz, 25MHz Span (Notes 4, 7) fCLK = 50MSPS, fOUT = 2.51MHz, 25MHz Span (Notes 4, 7) fCLK = 50MSPS, fOUT = 1.00MHz, 25MHz Span (Notes 4, 7) fCLK = 25MSPS, fOUT = 5.02MHz, 25MHz Span (Notes 4, 7) VOLTAGE REFERENCE Internal Reference Voltage, VFSADJ Internal Reference Voltage Drift Internal Reference Output Current Sink/Source Capability Reference Input Impedance Reference Input Multiplying Bandwidth (Note 7) DIGITAL INPUTS D7-D0, CLK Input Logic High Voltage with 5V Supply, VIH Input Logic High Voltage with 3V Supply, VIH Input Logic Low Voltage with 5V Supply, VIL Input Logic Low Voltage with 3V Supply, VIL Input Logic Current, IIH Input Logic Current, IIL Digital Input Capacitance, CIN (Note 3) (Note 3) (Note 3) (Note 3) 3.5 2.1 -10 -10 5 3 0 0 5 1.3 0.9 +10 +10 V V V V A A pF Voltage at Pin 18 with Internal Reference 1.04 1.16 60 0.1 1 1.4 1.28 V
ppm/oC
AVDD = DVDD = +5V, VREF = Internal 1.2V, IOUTFS = 20mA, TA = 25oC for All Typical Values (Continued) TA = -40oC TO 85oC TEST CONDITIONS MIN TYP MAX UNITS
-
70 73 67 51 61 48 56 68 68
-
dBc dBc dBc dBc dBc dBc dBc dBc dBc
-
62 73 74 67 68 54 60 53 67 68 68 71
-
dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc
A M MHz
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HI5660
Electrical Specifications
PARAMETER TIMING CHARACTERISTICS Data Setup Time, tSU Data Hold Time, tHLD Propagation Delay Time, tPD CLK Pulse Width, tPW1 , tPW2 AVDD Power Supply DVDD Power Supply Analog Supply Current (IAVDD) Digital Supply Current (IDVDD) Supply Current (IAVDD) Sleep Mode Power Dissipation See Figure 3 (Note 3) See Figure 3 (Note 3) See Figure 3 See Figure 3 (Note 3) 3 3 4 1 ns ns ns ns AVDD = DVDD = +5V, VREF = Internal 1.2V, IOUTFS = 20mA, TA = 25oC for All Typical Values (Continued) TA = -40oC TO 85oC TEST CONDITIONS MIN TYP MAX UNITS
POWER SUPPLY CHARACTERISTICS (Note 8, 9) (Note 8, 9) 5V or 3V, IOUTFS = 20mA 5V or 3V, IOUTFS = 2mA 5V, IOUTFS = Don't Care (Note 5) 3V, IOUTFS = Don't Care (Note 5) 5V or 3V, IOUTFS = Don't Care 5V, IOUTFS = 20mA (Note 6) 5V, IOUTFS = 20mA (Note 10) 5V, IOUTFS = 2mA (Note 6) 3.3V, IOUTFS = 20mA (Note 10) 3V, IOUTFS = 20mA (Note 6) 3V, IOUTFS = 20mA (Note 10) 3V, IOUTFS = 2mA (Note 6) Power Supply Rejection NOTES: 2. Gain Error measured as the error in the ratio between the full scale output current and the current through RSET (typically 625A). Ideally the ratio should be 32. 3. Parameter guaranteed by design or characterization and not production tested. 4. Spectral measurements made with differential transformer coupled output and no external filtering. 5. Measured with the clock at 50MSPS and the output frequency at 1MHz. 6. Measured with the clock at 100MSPS and the output frequency at 40MHz. 7. See `Definition of Specifications'. 8. It is recommended that the output current be reduced to 12mA or less to maintain optimum performance for operation below 3V. DVDD and AVDD do not have to be equal . 9. For operation above 125MHz, it is recommended that the power supply be 3.3V or greater. The part is functional with the clock above 125MSPS and the power supply below 3.3V, but performance is degraded. 10. Measured with the clock at 60MSPS and the output frequency at 10MHz. Single Supply (Note 7) 2.7 2.7 -0.2 5.0 5.0 23 4 3 1.5 1.6 165 150 70 75 85 67 27 5.5 5.5 30 5 3 +0.2 V V mA mA mA mA mA mW mW mW mW mW mW mW % FSR/V
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HI5660 Timing Diagrams
CLK
50%
D7-D0 V
1/ LSB ERROR BAND 2
GLITCH AREA = 1/2 (H x W)
HEIGHT (H)
IOUT WIDTH (W) tSETT tPD t(ps)
FIGURE 1. OUTPUT SETTLING TIME DIAGRAM
FIGURE 2. PEAK GLITCH AREA (SINGLET) MEASUREMENT METHOD
tPW1
tPW2
CLK tSU tHLD D7-D0 tSU tHLD tSU tHLD
50%
tPD
tSETT
IOUT
tPD
tSETT
tPD
tSETT
FIGURE 3. PROPAGATION DELAY, SETUP TIME, HOLD TIME AND MINIMUM PULSE WIDTH DIAGRAM
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HI5660 Definition of Specifications
Integral Linearity Error, INL, is the measure of the worst case point that deviates from a best fit straight line of data values along the transfer curve. Differential Linearity Error, DNL, is the measure of the step size output deviation from code to code. Ideally the step size should be 1 LSB. A DNL specification of 1 LSB or less guarantees monotonicity. Output Settling Time, is the time required for the output voltage to settle to within a specified error band measured from the beginning of the output transition. In the case of the HI5660, the measurement was done by switching from code 0 to 64, or quarter scale. Termination impedance was 25 due to the parallel resistance of the output 50 and the oscilloscope's 50 input. This also aids the ability to resolve the specified error band without overdriving the oscilloscope. Singlet Glitch Area, is the switching transient appearing on the output during a code transition. It is measured as the area under the overshoot portion of the curve and is expressed as a Volt-Time specification. Full Scale Gain Error , is the error from an ideal ratio of 32 between the output current and the full scale adjust current (through RSET). Full Scale Gain Drift, is measured by setting the data inputs to all ones and measuring the output voltage through a known resistance as the temperature is varied from TMIN to TMAX . It is defined as the maximum deviation from the value measured at room temperature to the value measured at either TMIN or MAX . The units are ppm of FSR (full scale range) per degree C. Total Harmonic Distortion, THD, is the ratio of the DAC output fundamental to the RMS sum of the first five harmonics. Spurious Free Dynamic Range, SFDR, is the amplitude difference from the fundamental to the largest harmonically or non-harmonically related spur within the specified window. Output Voltage Compliance Range, is the voltage limit imposed on the output. The output impedance load should be chosen such that the voltage developed does not violate the compliance range. Offset Error, is measured by setting the data inputs to all zeros and measuring the output voltage through a known resistance. Offset error is defined as the maximum deviation of the output current from a value of 0mA. Offset Drift, is measured by setting the data inputs to all zeros and measuring the output voltage through a known resistance as the temperature is varied from TMIN to MAX . It is defined as the maximum deviation from the value measured at room temperature to the value measured at either TMIN or TMAX . The units are ppm of FSR (full scale range) per degree C. Power Supply Rejection, is measured using a single power supply. Its nominal +5V is varied 10% and the change in the DAC full scale output is noted. Reference Input Multiplying Bandwidth, is defined as the 3dB bandwidth of the voltage reference input. It is measured by using a sinusoidal waveform as the external reference with the digital inputs set to all 1s. The frequency is increased until the amplitude of the output waveform is 0.707 of its original value. Internal Reference Voltage Drift, is defined as the maximum deviation from the value measured at room temperature to the value measured at either TMIN or TMAX . The units are ppm per degree C.
Detailed Description
The HI5660 is an 8-bit, current out, CMOS, digital to analog converter. Its maximum update rate is 125MSPS and can be powered by either single or dual power supplies in the recommended range of +3V to +5V. It consumes less than 165mW of power when using a +5V supply with the data switching at 100MSPS. The architecture is based on a segmented current source arrangement that reduces glitch by reducing the amount of current switching at any one time. The five MSBs are represented by 31 major current sources of equivalent current. The three LSBs are comprised of binary weighted current sources. Consider an input pattern to the converter which ramps through all the codes from 0 to 255. The three LSB current sources would begin to count up. When they reached the all high state (decimal value of 7) and needed to count to the next code, they would all turn off and the first major current source would turn on. To continue counting upward, the 3 LSBs would count up another 7 codes, and then the next major current source would turn on and the three LSBs would all turn off. The process of the single, equivalent, major current source turning on and the three LSBs turning off each time the converter reaches another 7 codes greatly reduces the glitch at any one switching point. In previous architectures that contained all binary weighted current sources or a binary weighted resistor ladder, the converter might have a substantially larger amount of current turning on and off at certain, worstcase transition points such as midscale and quarter scale transitions. By greatly reducing the amount of current switching at certain `major' transitions, the overall glitch of the converter is dramatically reduced, improving settling times and transient problems.
Digital Inputs and Termination
The HI5660 digital inputs are guaranteed to CMOS levels. However, TTL compatibility can be achieved by lowering the supply voltage to 3V due to the digital threshold of the input buffer being approximately half of the supply voltage. The internal register is updated on the rising edge of the clock. To minimize reflections, proper termination should be implemented. If the lines driving the clock and the digital
7
HI5660
inputs are 50 lines, then 50 termination resistors should be placed as close to the converter inputs as possible connected to the digital ground plane (if separate grounds are used).
Outputs
IOUTA and IOUTB are complementary current outputs. The sum of the two currents is always equal to the full scale output current minus one LSB. If single ended use is desired, a load resistor can be used to convert the output current to a voltage. It is recommended that the unused output be either grounded or equally terminated. The voltage developed at the output must not violate the output voltage compliance range of -0.3V to 1.25V. RLOAD should be chosen so that the desired output voltage is produced in conjunction with the output full scale current, which is described above in the `Reference' section. If a known line impedance is to be driven, then the output load resistor should be chosen to match this impedance. The output voltage equation is: VOUT = IOUT X RLOAD . These outputs can be used in a differential-to-single-ended arrangement to achieve better harmonic rejection. The SFDR measurements in this data sheet were performed with a 1:1 transformer on the output of the DAC (see Figure 1). With the center tap grounded, the output swing of pins 21 and 22 will be biased at zero volts. It is important to note here that the negative voltage output compliance range limit is -300mV, imposing a maximum of 600mVP-P amplitude with this configuration. The loading as shown in Figure 1 will result in a 500mV signal at the output of the transformer if the full scale output current of the DAC is set to 20mA.
Ground Plane(s)
If separate digital and analog ground planes are used, then all of the digital functions of the device and their corresponding components should be over the digital ground plane and terminated to the digital ground plane. The same is true for the analog components and the analog ground plane.
Noise Reduction
To minimize power supply noise, 0.1F capacitors should be placed as close as possible to the converter's power supply pins, AVDD and DVDD . Also, should the layout be designed using separate digital and analog ground planes, these capacitors should be terminated to the digital ground for DVDD and to the analog ground for AVDD . Additional filtering of the power supplies on the board is recommended.
Voltage Reference
The internal voltage reference of the device has a nominal value of +1.2V with a 60 ppm / oC drift coefficient over the full temperature range of the converter. It is recommended that a 0.1F capacitor be placed as close as possible to the REFIO pin, connected to the analog ground. The REFLO pin (16) selects the reference. The internal reference can be selected if pin 16 is tied low (ground). If an external reference is desired, then pin 16 should be tied high (to the analog supply voltage) and the external reference driven into REFIO, pin 17. The full scale output current of the converter is a function of the voltage reference used and the value of RSET. IOUT should be within the 2mA to 20mA range, through operation below 2mA is possible, with performance degradation. If the internal reference is used, VFSADJ will equal approximately 1.16V (pin 18). If an external reference is used, VFSADJ will equal the external reference. The calculation for IOUT (full scale) is: IOUT (Full Scale) = (VFSADJ/RSET) x 32. If the full scale output current is set to 20mA by using the internal voltage reference (1.16V) and a 1.86k RSET resistor, then the input coding to output current will resemble the following:
TABLE 1. INPUT CODING vs OUTPUT CURRENT INPUT CODE (D7-D0) 1111 1111 1000 0000 0000 0000 IOUTA (mA) 20 10 0 IOUTB (mA) 0 10 20
50 PIN 21 PIN 22 HI5660 IOUTB 100 IOUTA 50
VOUT = (2 x IOUT x REQ)V
50
FIGURE 4.
VOUT = 2 x IOUT x REQ, where REQ is ~12.5.
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HI5660 Pin Descriptions
PIN NO. 1-8 9-14 15 16 17 18 19 20 21 22 23 PIN NAME D7 (MSB) Through D0 (LSB) DCOM SLEEP REFLO REFIO FSADJ COMP1 ACOM IOUTB IOUTA NC PIN DESCRIPTION Digital Data Bit 7 (Most Significant Bit) through Digital Data Bit 0, (Least Significant Bit). Connect to digital ground. Control Pin for Power-Down mode. Sleep Mode is active high; Connect to ground for Normal Mode. Sleep pin has internal 20A active pulldown current. Connect to analog ground to enable internal 1.2V reference or connect to AVDD to disable internal reference. Reference voltage input if internal reference is disabled. Reference voltage output if internal reference is enabled. Use 0.1F cap to ground when internal reference is enabled. Full Scale Current Adjust. Use a resistor to ground to adjust full scale output current. Full Scale Output Current = 32 x VFSADJ/RSET. For use in reducing bandwidth/noise. Recommended: connect 0.1F to AVDD . Analog Ground. The complimentary current output of the device. Full scale output current is achieved when all input bits are set to binary 0. Current output of the device. Full scale output current is achieved when all input bits are set to binary 1. Internally connected to ACOM via a resistor. Recommend leave disconnected. Adding a capacitor to ACOM for upward compatibility is valid. Grounding to ACOM is valid. (For upward compatibility to 12-bit and 14-bit devices, pin 23 needs the ability to have a 0.1F capacitor to ACOM.) Analog Supply (+3V to +5V). No Connect (for upward compatibility to 12 and 14b, pin 25 needs to be grounded to ACOM). Digital Ground. Digital Supply (+3V to +5V). Input for clock. Positive edge of clock latches data.
24 25 26 27 28
AVDD NC DCOM DVDD CLK
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